In resent years, as an image sensor device, relative to a conventional CCD image sensor, a CMOS image sensor has been widespread, ranging from one for mobile phones to digital cameras, because of its advantages of low voltage and low power consumption and the easiness of merging with peripheral circuits.
FIG. 12 is a diagram illustrating a structure of a conventional CMOS image sensor 4. A general structure of the conventional CMOS image sensor is such that pixel circuits 100 are arranged in rows and columns, and a common power line 113 to which a pixel common voltage VD is supplied, a row scanning circuit 110, and column signal lines 111 are connected to each pixel circuit 100. Control and drive of the pixel circuits 100 are performed by the row scanning circuit 110 on a row-by-row basis. Each column signal line 111 is connected to a constant current source 120 and an AD converter 130 that performs AD conversion. After a voltage on the column signal line 111 is compared by a comparator 131 in the AD converter 130 with a ramp wave generated by a ramp wave generator 140, a memory portion 133 converts a result of the comparison into a digital code using a counter circuit 135 and records the digital code corresponding to the amount of light.
FIG. 2 shows an example of a configuration of a pixel circuit 100. The pixel circuit 100 includes a photodiode (PD) portion 101 that performs photoelectric conversion; a transfer gate transistor 102; a floating diffusion (FD) portion 103 that temporarily holds, through the transfer gate transistor 102, charge generated corresponding to light; a transistor 104 composing a source follower circuit that outputs a voltage of the FD portion 103 as a voltage to a column signal line 111; and a reset transistor 105 that resets the FD portion 103 to a certain voltage. A drain terminal of the transistor 104 composing a source follower circuit is connected to a common power line 113, by which a pixel common voltage VD is supplied.
For a method of reading the amount of charge, a correlated double sampling (CDS) scheme is commonly used. In the CDS scheme, a voltage (reset level) on the column signal line 111 in which a voltage of the FD portion 103 obtained before transferring charge is reflected is read, and a voltage is applied to the transfer gate transistor 102 to transfer charge, and then, a voltage (signal level) on the column signal line 111 in which a voltage of the FD portion 103 having decreased due to the transfer of the charge is reflected is read, by which the differential voltage between the reset level and the signal level is calculated as a digital code that reflects the amount of light.
Meanwhile, there is known a blackening phenomenon where, when, for example, intense light, e.g., the sun, is captured by a CMOS image sensor, despite the fact that an image is such that the sun portion is supposed to output the full code, a blackened image is displayed. A detail of the reason therefor is described below.
FIG. 13 is a timing chart showing the operations performed by control lines (an RST wiring line, a VR wiring line, and a TX wiring line) for a row from which charge is read, and changes in a voltage VS on a column signal line 111 for when a pixel circuit 100 receives normal light and when the pixel circuit 100 receives intense light.
After the FD portion 103 is reset during a period T1, a reset level voltage Vrst is sampled in the latter part of a period T2. When charge is transferred from the PD portion 101 to the FD portion 103 during a period T3, a signal level Vsig is sampled during a period T4. Then, a voltage Vele=Vrst−Vsig corresponding to the amount of light is converted into a digital code value.
However, it is known that, as indicated by a dashed line in FIG. 13, when the PD portion 101 receives intense light, the voltage VS on the column signal line 111 decreases from the time of reset level sampling which is before transferring charge. In this case, since Vele becomes substantially 0, it is erroneously judged that it is black (=a dark state).
To avoid this blackening phenomenon, various methods have been proposed so far.
Patent Document 1 discloses a digital CDS method. Digital CDS is a method in which first a reset level voltage is AD-converted and then a signal level voltage is AD-converted, by which the difference between the reset level and signal level digital values is calculated as a digital code proportional to the amount of light.
As measures to avoid a blackening phenomenon in the digital CDS, in Patent Document 1 an intense light judgment is made during a reset level sampling period. When intense light enters, a reset level voltage to be sampled during the reset level sampling period decreases. The method is such that, when the voltage goes out of a ramp-wave reference voltage range which is assumed to perform AD conversion, the light is judged to be intense light and a result thereof is reflected in a digital code.
In addition, Patent Document 2 proposes a method of controlling a digital code by temporarily saving a reset level voltage in a sampling capacitance and comparing the reset level voltage with a reference voltage by a latch circuit to make a judgment of normal light and intense light by whether the reset level voltage is higher or lower than the reference voltage.
Patent Document 3 proposes a method in which after a sampling period for a reset level voltage and a signal level voltage ends, the signal level voltage is compared with a blackening judgment voltage generated by a correction bias circuit.